The present invention relates to components of semiconductor integrated circuits and, in particular, to the utilization of a small transistor to provide a high impedance device for biasing the well under a dual plate integrated capacitor.
Capacitors are a common device in integrated circuits. The dual polysilicon, or poly-poly, capacitor is used extensively in circuits designed in MOS processes. The main disadvantage of all integrated capacitors, including poly-poly capacitors, is a relatively small capacitance per area that requires large expensive devices for even modest capacitance values. An additional problem of dual plate, poly-poly capacitor structures is an unwanted parasitic capacitance between the lower poly plate and the underlying silicon substrate that can affect circuit performance and couple noise to and from the substrate. It is well known that these effects may be minimized by placing an electrically charged well beneath the capacitor structure. It is also well known that the well can be a source of noise for the biasing source unless a series impedance is placed between the well and the voltage source. This technique requires a large value resistance to function effectively, which in turn requires a large amount of die area devoted to the biasing resistor.
The present invention utilizes a small MOS transistor to replace the large resistor utilized in conventional dual plate capacitor designs, thus saving considerable die area.
More specifically, an integrated dual-plate capacitor structure in accordance with the present invention includes a semiconductor substrate having a first conductivity type and having a well region having a second conductivity type opposite the first conductivity type formed therein. An upper conductive plate and a lower conductive plate separated by a first layer of dielectric material are formed over the well region. The lower capacitor plate is separated from the upper surface of the well region by a second layer of dielectric material. A MOS transistor is formed in the semiconductor substrate. The MOS transistor includes space-apart source and drain regions of the second conductivity type that define a substrate channel region therebetween. A conductive gate is formed above the channel region and is separated therefrom by a layer of intervening dielectric material. The source region and the gate of the MOS transistor are connected to receive a bias voltage. The drain region of the MOS transistor is electrically connected to the well region.
In an alternative embodiment of the invention, the drain of the MOS transistor is incorporated into the well region of the capacitor structure.